Method of forming inter-dielectric layer in semiconductor device

ABSTRACT

The present invention relates to a method of forming an interlayer dielectric film in a semiconductor device. More particularly, the present invention selectively forms an insulating film spacer only at a region where a plug is formed between metal lines and removes the insulating film spacer at a region where the plug is not formed to lower the aspect ratio between the metal lines, in a process of burying an insulating material between the metal lines to electrically insulate them. Therefore, the present invention can easily bury the insulating material even between the metal lines having a narrow gap without voids.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The invention relates generally to a method of forming aninterlayer dielectric film in a semiconductor device, and moreparticularly to, a method of forming an interlayer dielectric film in asemiconductor device capable of easily burying an insulating materialeven between metal lines having a narrow gap without voids, in a processof burying the insulating material between the metal lines in order toelectrically insulate them.

[0003] 2. Description of the Prior Art

[0004] As a next-generation DRAM is developed, the length of a MOSFETchannel used is significantly reduced and the minimum pitch size of wordlines and bit lines is also gradually reduced. In a multi-layer metalstructure system such as DRAM, further, a method by an insulating spaceris formed on the sidewall of a metal line using nitride or oxide inorder to insulate the metal line and a metal plug, has been widely used,which further reduces the distance between the metal lines. In thiscase, upon deposition of IMD (inter metal dielectric is deposition), agap filling comes to the front as a serious problem.

[0005]FIG. 1 shows a layout of a general 8F2 DRAM after the word linesand the bit lines are formed, FIGS. 2A˜2C are cross-sectional views ofthe device taken along lines A-A′, B-B′ and C-C′ in FIG. 1, and FIGS.3A˜3C are cross-sectional views of the device taken along lines A-A′,B-B′ and C-C′ in FIG. 1.

[0006] Referring now to FIG. 1, FIGS. 2A˜2C and FIGS. 3A˜3C, a word line13, a word line spacer 14, a first interlayer dielectric film 15, a bitline plug 16, bit lines 17, bit line spacers 18, second interlayerdielectric films 19 and a contact plug 20 are sequentially formed on asemiconductor substrate 11 in which a device isolation film 12 isformed, through a common process.

[0007] As mentioned above, In a multi-layer metal structure system suchas DRAM, further, a method by an insulating spacer (word line spacer orbit line spacer) is formed on the sidewall of a metal line using nitrideor oxide in order to insulate the metal lines (bit lines or word lines)and a metal plug (bit line plug or contact plug), has been widely used,which thus requires a higher integration of the device and furtherreduces the distance between the metal lines.

[0008]FIGS. 4A and 4B are cross-sectional views of the device forexplaining a gap filling problem depending on an increased aspect ratio;

[0009] Referring to FIG. 1 and FIG. 4A, in order to manufacture a DRAM,a word line 13, a word line spacer 14, a first interlayer dielectricfilm 15, a bit line plug 16, bit lines 17 and bit line spacers 18 areformed on a semiconductor substrate 11 in which a device isolation film12 is formed, through a common process.

[0010] At this time, the distance “W” between the bit lines 17 isreduced by the width “L” of the bit line spacer, so that an actualdistance “W” between the bit lines is “W-2L”.

[0011] Referring to FIG. 1 and 4B, with the bit lines 17 and the bitline spacer 18 formed, a second interlayer dielectric film 19 is formedon the entire surface for an electrical insulation with upper elements.

[0012] At this time, as the aspect ratio between the bit lines 17 isincreased by the bit line spacer 18 and the speed where the secondinterlayer dielectric films 19 are formed below between the bit lines 17is therefore further faster than that where the second interlayerdielectric films 19 are formed over the bit lines 17, voids A aregenerated below between the bit lines 17. This degrades an electricalcharacteristic of the device and reliability of the process.

SUMMARY OF THE INVENTION

[0013] The present invention is contrived to solve the above problemsand an object of the present invention is to provide a method of formingan interlayer dielectric film in a semiconductor device, which canimprove a burial characteristic between metal lines, in a way that aninsulating film spacer is selectively formed only at a region where aplug is formed between the metal lines and the insulating film spacer ata region where the plug is not formed is removed to lower the aspectratio between the metal lines.

[0014] In order to accomplish the above object, a method of forming aninterlayer dielectric film in a semiconductor device according to afirst embodiment of the present invention is characterized in that itcomprises the steps of forming conductive layer patterns of a givenpattern and an insulating film spacer on the sidewalls of the conductivelayer patterns through a common process; removing the insulating filmspacer formed in a region other than a region where a contact plug willbe formed; and forming an interlayer dielectric film on the entiresurface.

[0015] A method of forming an interlayer dielectric film in asemiconductor device according to a second embodiment of the presentinvention is characterized in that it comprises the steps of formingconductive layer patterns of a given pattern through a common process;forming an interlayer dielectric film on the entire surface; andremoving the interlayer dielectric film at a region where a contact plugwill be formed and then forming an insulating film spacer on thesidewall of the conductive layer patterns.

[0016] A method of forming an interlayer dielectric film in asemiconductor device according to a third embodiment of the presentinvention is characterized in that it comprises the steps of formingconductive layer patterns of a given pattern and an insulating filmspacer on the sidewall of the conductive layer patterns through a commonprocess; burying a conductive material between the conductive layerpatterns; removing the conductive material only at a given region andremaining the conductive material at remaining regions to form a contactplug; and burying an interlayer dielectric film between the conductivelayer patterns at a region from which the conductive material isremoved.

[0017] In the above, the conductive layer patterns may be word lines orbit lines.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The aforementioned aspects and other features of the presentinvention will be explained in the following description, taken inconjunction with the accompanying drawings, wherein:

[0019]FIG. 1 shows a layout of a general DRAM device;

[0020] FIGS. 2A˜2C are cross-sectional views of the device taken alonglines A-A′, B-B′ and C-C′ in FIG. 1;

[0021] FIGS. 3A˜3C are cross-sectional views of the device taken alonglines A-A′, B-B′ and C-C′ in FIG. 1;

[0022]FIGS. 4A and 4B are cross-sectional views of the device forexplaining a gap filling problem depending on an increased aspect ratio;

[0023]FIGS. 5A and 5B show layouts for explaining a method of forming aninterlayer dielectric film in a semiconductor device according to oneembodiment of the present invention; and

[0024] FIGS. 6A˜6C are cross-sectional views of a device for explaininga method of forming an interlayer dielectric film in a semiconductordevice according to another embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

[0025] The present invention will be described in detail by way of apreferred embodiment with reference to accompanying drawings.

[0026]FIGS. 5A and 5B show layouts for explaining a method of forming aninterlayer dielectric film in a semiconductor device according to oneembodiment of the present invention.

[0027] Referring now to FIG. 5A, a device isolation film (not shown), ajunction region 51 a, word lines 53 and a word line spacer 54 are formedon a semiconductor substrate through a common process. Then, a firstphotoresist pattern 60 is formed at a region wherein a contact plug willbe formed, for the purpose of an electrical insulation with upperelements including a capacitor to be formed in a subsequent process. Thefirst photoresist pattern 60 is formed to sufficiently cover the wordline spacer 54 in a region where a contact plug will be formed.Thereafter, an exposed portion of the word line spacer 54 is removed byetch process. Thereby, the word line spacer 54 remains on the sidewallof the word lines 53, with the contact plug and the word lines 53 havinga margin that will not be electrically connected together at a regionwhere the contact plug will be formed. Next, a first interlayerdielectric film (not shown) is formed on the entire surface in order toelectrically insulate the word lines 53 and bit lines that will beformed in a subsequent process. The word line spacer is removed fromremaining regions other than a region that the contact plug will beformed so that the distance between the word lines 53 can besufficiently secured to lower the aspect ratio. Therefore, the firstinterlayer dielectric film can be easily buried between the word lines53 without any voids. As the first interlayer dielectric film must beremoved from the region where the word line spacer 54 remains in orderto form the contact plug in a subsequent process, there is no problemeven when voids are generated in the first interlayer dielectric film inthis region. After the word line spacer is removed, the firstphotoresist pattern 60 is removed.

[0028] Referring now to FIG. 5B, a bit line plug (formed below the bitline, not shown), bit lines 57 and a bit line spacer 58 are sequentiallyformed at a given region on the first interlayer dielectric film (notshown) formed on the entire surface, through a common process. For thepurpose of an electrical isolation with upper elements including acapacitor to be formed in a subsequent process, a second photoresistpattern 61 is formed at a region where the contact plug will be formed.The second photoresist pattern 61 is formed to sufficiently cover thebit line spacer 58 in the region where the contact plug will be formed.The exposed bit line spacer 58 is then removed by etch process. Thereby,the bit line spacer 58 remains on the sidewall of the bit lines 57, withthe contact plug and the bit lines 57 having a margin that will not beelectrically connected together at a region where the contact plug willbe formed. Next, a second interlayer dielectric film (not shown) isformed on the entire surface in order to electrically insulate the bitlines 57 and upper elements including a capacitor that will be formed ina subsequent process. The bit line spacer is removed from remainingregions other than a region that the contact plug will be formed, sothat the distance between the bit lines 57 can be sufficiently securedto lower the aspect ratio. Therefore, the second interlayer dielectricfilm can be easily buried between the bit lines 57 without any voids.Similarly, as the second interlayer dielectric film must be removed fromthe region where the bit line spacer 58 remains in order to form thecontact plug in a subsequent process, there is no problem even whenvoids are generated in the second interlayer dielectric film in thisregion. After the bit line spacer is removed, the second photoresistpattern 61 is removed.

[0029] Thereafter, though not shown in the drawings, the second andfirst interlayer dielectric films are removed to expose the junctionregion of the semiconductor substrate. Then, a conductive material isburied to form the contact plug and upper elements including thecapacitor are formed through a common process.

[0030] The above process forms an insulating film spacer at the sidewallof the word lines or the bit lines, removing the insulating film spacerin a region where the plug is not formed and buries the interlayerdielectric film, thus securing the distance between the word lines orthe bit lines to improve a burial characteristic of the interlayerdielectric film.

[0031] Also, another embodiment for securing the distance between theword lines or the bit lines by removing an insulating film spacer in aregion where the plug is not formed will be below explained.

[0032] After the word lines or the bit lines are formed through a commonprocess, an interlayer dielectric film is completely buried between theword lines or the bit lines before an insulating film spacer is formed.At this time, as the distance between the word lines or the bit lines issufficiently secured since the insulating film spacer is not formed,between the word lines or the bit lines can be easily buried using theinterlayer dielectric film without voids. Thereafter, after only aninterlayer dielectric film in a region where the plug will be formed isremoved, an insulating film spacer is formed on the sidewall of the wordlines or the bit lines, which is exposed by the removed interlayerdielectric film.

[0033] In addition, still another embodiment for securing the distancebetween the word lines or the bit lines by removing an insulating filmspacer in a region where the plug is not formed will be below explained.

[0034] FIGS. 6A˜6C are cross-sectional views of a device for explaininga method of forming an interlayer dielectric film in a semiconductordevice according to another embodiment of the present invention.

[0035] Referring now to FIG. 6A, word lines (not shown), a word linespacer (not shown) and a junction region (not shown) are formed on asemiconductor substrate 71 in which a device isolation region 72 isformed at a given region, through a common process. Then, a firstinterlayer dielectric film 73 is formed on the entire surface. After thefirst interlayer dielectric film 73 on the junction region is removed byetch process, a conductive material is buried into a region from whichthe first interlayer dielectric film 73 is removed to form a firstcontact plug 74, in order to electrically connected the junction regionand upper elements to be formed in a subsequent process. Next,insulating films of a given pattern such as bit lines 75 and a nitridefilm 76 are sequentially formed on the first interlayer dielectric film73 and an insulating film spacer 77 is then formed on the sidewall ofthe bit line 75 and the nitride film 76. At this time, an upper surfaceof the first contact plug 74 is exposed between the bit lines 75. Then,after polysilicon or a conductive material is formed on the entiresurface, polysilicon or the conductive material on the nitride film isremoved by means of planarization process, so that it remains onlybetween the bit lines 75, thus forming a second contact plug 78. If thesecond contact plug 78 is formed between the bit lines 75, a photoresistpattern 79 of a given pattern is formed on the entire surface to exposeonly an unnecessary portion of the second contact plug.

[0036] Referring now to FIG. 6B, the unnecessary portion of the secondcontact plug is removed by etching process and the exposed insulatingfilm spacer 77 is removed while the second contact plug is removed.Then, the photoresist pattern is removed.

[0037] Thereby, the second and first contact plugs 78 and 74electrically connect an upper element such as a capacitor, etc., thatwill be formed in a subsequent process, to the junction region.

[0038] Referring now to FIG. 6C, a second interlayer dielectric film 80is formed on the entire surface. Then, a planarization process such aschemical mechanical polishing process, and the like is implemented tobury the second interlayer dielectric film 80 between the bit lines 75from which the second contact plug and the insulating film spacer aremoved to electrically isolate the bit lines 75.

[0039] The insulating film spacer is removed from between the bit lines75 in which the second interlayer dielectric film 80 is buried, thuslowering the aspect ratio. Therefore, the second interlayer dielectricfilm 80 can be easily buried without voids.

[0040] Though the above methods can easily bury an insulating materialbetween word lines or bit lines having a narrow width in a memorydevice, they can also easily bury the insulating film between metallines or patterns having a narrow width.

[0041] As mentioned above, the present invention can easily bury aninsulating material between metal lines without voids by selectivelyforming an insulating film spacer only at a given region. Therefore, thepresent invention has an advantage that it can improve reliability ofthe process and an electrical characteristic of the device.

[0042] The present invention has been described with reference to aparticular embodiment in connection with a particular application. Thosehaving ordinary skill in the art and access to the teachings of thepresent invention will recognize additional modifications andapplications within the scope thereof.

[0043] It is therefore intended by the appended claims to cover any andall such applications, modifications, and embodiments within the scopeof the present invention.

What is claimed is:
 1. A method of forming an interlayer dielectric filmin a semiconductor device, comprising the steps of: forming aninsulating film spacer only on the sidewall of conductive layer patternsat a region where a contact plug will be formed and then forming aninterlayer dielectric film on the entire surface.
 2. The method offorming an interlayer dielectric film in a semiconductor device asclaimed in claim 1, wherein said conductive layer patterns are wordlines or bit lines.
 3. A method of forming an interlayer dielectric filmin a semiconductor device, comprising the steps of: forming conductivelayer patterns of a given pattern and an insulating film spacer on thesidewalls of said conductive layer patterns through a common process;removing said insulating film spacer formed in a region other than aregion where a contact plug will be formed; and forming an interlayerdielectric film on the entire surface.
 4. The method of forming aninterlayer dielectric film in a semiconductor device as claimed in claim3, wherein said conductive layer patterns are word lines or bit lines.5. A method of forming an interlayer dielectric film in a semiconductordevice, comprising the steps of: forming conductive layer patterns of agiven pattern through a common process; forming an interlayer dielectricfilm on the entire surface; and removing said interlayer dielectric filmat a region where a contact plug will be formed and then forming aninsulating film spacer on the sidewall of said conductive layerpatterns.
 6. The method of forming an interlayer dielectric film in asemiconductor device as claimed in claim 5, wherein said conductivelayer patterns are word lines or bit line.
 7. A method of forming aninterlayer dielectric film in a semiconductor device, comprising thesteps of: forming conductive layer patterns of a given pattern and aninsulating film spacer on the sidewall of said conductive layer patternsthrough a common process; burying a conductive material between saidconductive layer patterns; removing said conductive material only at agiven region and remaining said conductive material at remaining regionsto form a contact plug; and burying an interlayer dielectric filmbetween said conductive layer patterns at a region from which saidconductive material is removed.
 8. The method of forming an interlayerdielectric film in a semiconductor device as claimed in claim 7, whereinsaid conductive layer patterns are word lines or bit lines.